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p re - production this is a product in the pre - production phase of development. device characterization is complete and ramtron does not expe ct to change the specifications . ramtron will issue a product change notice if any specification changes are made. cypress semiconductor cor poration ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 001 - 86209 rev. ** revised february 2 5 , 2013 fm 1808 b 256kb bytew ide 5v f - ram memory features 256kbit ferroelectric nonvolatile ram organized as 32,768 x 8 bits high endurance 1 trillion (10 1 2 ) read/writes 38 year data retention (@ 75c) nodelay? writes advanced high - reliability ferroelectric process superior to bbsram modules no battery concerns monolithic reliability true surface mount solution, no rework steps sup erior for moisture, shock, and vibration resistant to negative voltage undershoots sram & eeprom compatible jedec 32kx8 sram & eeprom pinout 70 ns access time 130 ns cycle time low power operation 1 5 ma active current 2 5 a (typ.) standby current industry standard configuration industrial temperature - 40 c to +85 c 28 - pin green/rohs soic package description the FM1808B is a 256 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile but operates in other respects as a ram. it provides data retention for 38 years while eliminating the reliabilit y concerns, functional disadvantages and system design complexities of battery - backed sram (bbsram). fast write timing and high write endurance make f - ram superior to other types of nonvolatile memory. in - system operation of the FM1808B is very similar t o other ram devices. minimum read - and write - cycle times are equal. the f - ram memory, however, is nonvolatile due to its unique ferroelectric memory process. unlike bbsram, the FM1808B is a truly monolithic nonvolatile memory. it provides the same function al benefits of a fast write without the disadvantages associated with modules and batteries or hybrid memory solutions. these capabilities make the FM1808B ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environm ent. the availability of a true surface - mount package improves the manufacturability of new des igns. device specifications are guaranteed over an industrial temperature range of - 40c to +85c. pin configuration ordering information FM1808B - sg 28 - pin green a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 vss dq 3 dq 4 dq 5 dq 6 dq 7 ce a 10 oe a 11 a 9 a 8 a 13 we vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 2 of 12 figure 1. block diagram pin description pin name type description a(14:0) input address: the 15 address lines select one of 32,768 bytes in the f - ram array. the address value is latched on the falling edge of /ce. dq(7:0) i/o data: 8 - bit bi - directional data bus for accessing the f - ram array. /ce input chip enable: /ce selects the device when low. asserting /ce low causes the address to be latched internally. address changes that occur after /ce goes low will be ignored until the next falling edge occurs. /oe input output enable: asserting /oe low caus es the FM1808B to drive the data bus when valid data is available. deasserting /oe high causes the dq pins to be tri - stated. /we input write enable: asserting /we low causes the FM1808B to write the contents of the data bus to the address location latched by the falling edge of /ce. vdd supply supply voltage : 5v vss supply ground functional truth table /ce /we function h x standby/precharge x latch address (and begin write if /we=low) l h read l write note: the /oe pin controls only the dq output buffers. address latch & decoder a ( 14 : 0 ) ce control logic we a ( 14 : 0 ) i / o latch bus driver oe 32 , 768 x 8 fram array dq ( 7 : 0 )
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 3 of 12 overview the FM1808B is a bytewide f - ram memory. the memory array is logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. all data written to the part is immediately nonvolatile with no delay. functional operation of the f - ram memory is the same as sra m type devices, except the FM1808B requires a falling edge of /ce to start each memory cycle. memory architecture users access 32,768 memory locations each with 8 data bits through a parallel interface. the complete 15 - bit address specifies each of the 32 ,768 bytes uniquely. internally, the memory array is organized into 4092 rows of 8 - bytes each. this block segmentation has no effect on operation, however the user may wish to group data into blocks by its endurance characteristics as explained on page 4. the cycle time is the same for read and write memory operations. this simplifies memory controller logic and timing circuits. likewise the access time is the same for read and write memory operations. when /ce is deasserted high, a precharge operation be gins, and is required of every memory cycle. thus unlike sram, the access and cycle times are not equal. writes occur immediately at the end of the access with no delay. unlike an eeprom, it is not necessary to poll the device for a ready condition since w rites occur at bus speed. it is the users responsibility to ensure that v dd remains within datasheet tolerances to prevent incorrect operation. also proper voltage level and timing relationships between v dd and /ce must be maintained during power - up an d power - down events. see power cycle timing diagram on page 9. memory operation the FM1808B is designed to operate in a manner similar to other bytewide memory products. for users familiar with bbsram, the performance is comparable but the bytewide interfa ce operates in a slightly different manner as described below. for users familiar with eeprom, the obvious differences result from the higher write performance of f - ram technology including nodelay writes and much higher write endurance. read operation a read operation begins on the falling edge of /ce. at this time, the address bits are latched and a memory cycle is initiated. once started, a full memory cycle must be completed internally even if /ce goes inactive. data becomes available on the bus afte r the access time has been satisfied. after the address has been latched, the address value may be changed upon satisfying the hold time parameter. unlike an sram, changing address values will have no effect on the memory operation after the address is l atched. the FM1808B will drive the data bus when /oe is asserted low. if /oe is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. if /oe is asserted prior to completion of the memory access, the data b us will not be driven until valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. when /oe is inactive the data bus will remain tri - stated. write operation writes occur in the FM1808B in the same time interval as reads. the FM1808B supports both /ce - and /we - controlled write cycles. in all cases, the address is latched on the falling edge of /ce. in a /ce controlled write, the /we signal is asserted prior t o beginning the memory cycle. that is, /we is low when /ce falls. in this case, the part begins the memory cycle as a write. the FM1808B will not drive the data bus regardless of the state of /oe. in a /we controlled write, the memory cycl e begins on the falling edge of /ce. the /we signal falls after the falling edge of /ce. therefore, the memory cycle begins as a read. the data bus will be driven according to the state of /oe until /we falls. the timing of both /ce - and /we - controlled write cycles is sh own in the electrical specifications. write access to the array begins asynchronously after the memory cycle is initiated. the write access terminates on the rising edge of /we or /ce, whichever is first. data set - up time, as shown in the electrical spec ifications, indicates the interval during which data cannot change prior to the end of the write access. unlike other truly nonvolatile memory technologies, there is no write delay with f - ram . since the read and write access times of the underlying memor y are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. therefore, any operation including read or write can occur immediately following a write. data polling, a technique used with eeproms t o determine if a write is complete, is unnecessary.
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 4 of 12 precharge operation the precharge operation is an internal condition that prepares the memory for a new access. all memory cycles consist of a memory access and a precharge. the precharge is initiated by deasserting the /ce pin high. it must remain high for at least the minimum precharge time t pc . the user determines the beginning of this operation since a precharge will not begin until /ce rises. however, the device has a maximum /ce low time specifica tion that must be satisfied. endurance internally, a f - ram operates with a read and restore mechanism. therefore, each read and write cycle involves a change of state. the memory architecture is based on an array of rows and columns. each read or write ac cess causes an endurance cycle for an entire row. in the FM1808B , a row is 64 bits wide. every 8 - byte boundary marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows. regardless, f - r am offers substantially higher write endurance than other nonvolatile memories. the rated endurance limit of 10 1 2 cycles will allow 3, 0 00 accesses per second to t he same row for over 1 0 years. f - ram design considerations when designing with f - ram for the first time, users of sram will recognize a few minor differences. first, bytewide f - ram memories latch each address on the falling edge of chip enable. this allows the address bus to change after starting the memory access. since every access latc hes the memory address on the falling edge of /ce, users cannot ground it as they might with sram. users who are modifying existing designs to use f - ram should examine the memory controller for timing compatibility of address and control pins. each memor y access must be qualified with a low transition of /ce. in many cases, this is the only change required. an example of the signal relationships is shown in figure 2 below. also shown is a common sram signal relationship that will not work for the FM1808B . the reason for /ce to strobe for each address is two - fold: it latches the new address and creates the necessary precharge period while /ce is high. figure 2. chip enable and memory address relationships valid strobing of /ce fram signaling ce address a1 a2 data d1 d2 invalid strobing of /ce sram signaling ce address a1 a2 data d1 d2
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 5 of 12 a second design consideration relates to the level of v dd during operation. battery - backed srams are forced to monitor v dd in order to switch to battery backup. they typically block user acce ss below a certain v dd level in order to prevent loading the battery with current demand from an active sram. the user can be abruptly cut off from access to the nonvolatile memory in a power down situation with no warning or indication. f - ram memories d o not need this system overhead. the memory will not block access at any v dd level that complies with the specified operating range. the user should take measures to prevent the processor from accessing memory when v dd is out - of - tolerance. the common desi gn practice of holding a processor in reset during powerdown may be sufficient. it is recommended that chip enable is pulled high and allowed to track v dd during powerup and powerdown cycles. it is the users responsibility to ensure that chip enable is hig h to prevent accesses below v dd min . ( 4.5 v). figure 3 shows a pullup resistor on /ce which will keep the pin high during power cycles assuming the mcu/mpu pin tri - states during the reset condition. the pullup resistor value should be chosen to ensure the /ce pin tracks v dd yet a high enough value that the current drawn when /ce is low is not an issue. figure 3. use of pullup resistor on /ce ce we oe a(14:0) dq fm 1808 b v dd mcu/ mpu r
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 6 of 12 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any pin with respect to v ss - 1.0v to +7.0v and v in < v dd +1.0v t stg storage temperature - 55 c to + 125 c t lead lead temperature (soldering, 10 seconds) 26 0 c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 2 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods ma y affect device reliability. dc operating conditions ( t a = - 40 c to + 85 c, v dd = 4.5 v to 5.5v unless otherwise specified) symbol parameter min typ max units notes v dd power supply 4.5 5.0 5.5 v i dd v dd supply current - 1 5 ma 1 i sb 1 standby current (ttl) - 1.8 m a 2 i sb2 standby current (cmos) 25 50 a 3 i li input leakage current - 1 a 4 i lo output leakage current - 1 a 4 v ih input high voltage 2.0 v dd +0.3 v v il input low voltage - 0.3 0.8 v v oh1 output high voltage ( i oh = - 2 ma) 2.4 v v oh2 output high voltage ( i oh = - 100 a) v dd - 0.2 v v ol1 output low voltage ( i ol = 4.2 ma) 0.4 v v ol2 output low voltage ( i ol = 150 a) 0.2 v notes 1. v dd = 5.5v, /ce cycling at minimum cycle time. all inputs at cmos levels, all outputs unloaded. 2. v dd = 5.5v, /ce at v ih , all other pins at ttl levels 3. v dd = 5.5v, /ce at v ih , all other pins at cmos levels (0.2v or v dd - 0.2v) . 4. v in , v out between v dd and v ss .
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 7 of 12 read cycle ac parameters ( t a = - 40 c to + 85 c, v dd = 4.5v to 5.5v , unless otherwise specified) symbol parameter min max units notes t ce chip enable access time (to data valid) 70 ns t ca chip enable active time 70 ns t rc read cycle time 130 ns t pc precharge time 60 ns t as address setup time 0 ns t ah address hold time 15 ns t oe output enable access time 12 ns t hz chip enable to output high - z 15 ns 1 t ohz output enable to output high - z 15 ns 1 write cycle ac parameters (t a = - 40 c to + 85 c, v dd = 4.5v to 5.5v unless otherwise specified) symbol parameter min max units notes t ca chip enable active time 70 ns t cw chip enable to write high 70 ns t wc write cycle time 130 ns t pc precharge time 60 ns t as address setup time 0 ns t ah address hold time 15 ns t wp write enable pulse width 40 ns t ds data setup 30 ns t dh data hold 0 ns t wz write enable low to output high z 15 ns 1 t wx write enable high to output driven 10 ns 1 t hz chip enable to output high - z 15 ns 1 t ws write enable setup 0 ns 2 t wh write enable hold 0 ns 2 notes 1 t his parameter is periodically sampled and not 100% tested . 2 the relationship between /ce and /we determines if a /ce - or /we - controlled write occurs. there is no timing specification associated with this relationship. data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 19 - years @ +75oc 38 - years
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 8 of 12 capacitance ( t a = 25 c, f=1.0 mhz, v dd = 5v) symbol parameter min max units notes c i/o input/ output capacitance (dq) - 8 pf c in input capacitance - 6 pf ac test conditions input pulse levels 0 to 3v input rise and fall times 10 ns input and output timing levels 1.5v read cycle timing write cycle timing - /ce controlled timing equivalent ac load circuit ce a0-14 oe dq0-7 t as t ah t ce t oe t ca t rc t pc t ohz t hz ce a0-14 we dq0-7 t as t ah t ca t wc t pc oe t ws t ds t dh t wh
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 9 of 12 write cycle timing - /we controlled timing power cycle timing power cycle timing (t a = - 40 c to + 85 c, v dd = 4.5 v to 5.5v unless otherwise specified) symbol parameter min max units notes t pu v dd (min) to first access start 1 0 - m s t pd last access complete to v dd (min) 0 - s t v r v dd rise time 3 0 - s/v 1 t vf v dd fall time 3 0 - s/v 1 notes 1. sl ope measured at any point on v dd waveform . ce a0-14 we dq0-7 out t as t ah t ca t wc t pc oe t ws t wh dq0-7 in t ds t wp t wz t wx t dh t c w v ih (min) t pd t pu v dd ce v il (max) v dd (min) t pc v dd (min) v ih (min) v ih (min) v ih (min) t pd t pd t pu t pu v dd ce v il (max) v il (max) v dd (min) v dd (min) t pc t pc v dd (min) v dd (min) v ih (min) v ih (min)
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 10 of 12 28 - pin soic (jedec ms - 013 variation ae) all dimensions in millimeters soic package marking scheme legend: xx xx xx= part number, p= package type ( - s g) r= rev code, yy=year, ww=work week, llllll = lot code example: FM1808B , 70ns speed, green /rohs soic package, a die rev., year 2010, work week 37 , lot code 00002g ramtron FM1808B - s g a103700002g ramtron xxxx xxx - p r yyww ll l ll l pin 1 7 . 50 0 . 10 10 . 30 0 . 30 17 . 90 0 . 20 0 . 10 0 . 30 2 . 35 2 . 65 0 . 33 0 . 51 1 . 27 typ 0 . 10 0 . 25 0 . 75 45 0 . 40 1 . 27 0 . 23 0 . 32 0 ? - 8 ?
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 11 of 12 revision history revision date summary 1.0 11/ 22 /2010 initial release 1.1 12/20 /2010 updated msl rating. 1.2 3/1 4 /2011 changed t pu and t vf spec limits. 2. 0 1/6/2012 changed to pre - production status. changed t vf spec. document history document title: FM1808B 256kb bytewide 5v f - ram memory document number: 001 - 8 620 9 revision ecn orig. of change submission date description of change ** 3912933 gvch 02/25/2013 new spec
fm 1808 b C 256kb bytewide 5v f - ram document number: 001 - 8620 9 rev. ** page 12 of 12 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go /a utomotive clocks & buffers cypress.com/go/clocks interface cypress.com/go /i nterface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support ramtron is a registered trademark and nodelay? is a trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semi conductor corporation, 2011 - 2013 . the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress p roduct. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medi cal, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypr ess. furthermore, cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in lif e - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is pro tected by and subject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cy press hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in support of licen see product to be used only in conjunction with a cypress integrated circuit as specifi ed in the applicable agreement. any reproduction, modification, translation, compilation, or representation of this source code except as specified above is prohibited without the express w ritten permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the material s described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize it s products for use as critical components in life - support systems where a malfunction o r failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement .

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